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advance cyw43143 single chip ieee 802.11 b/ g/n mac/phy/radio with usb/sdio host interface cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-15045 rev. *f revised april 20, 2017 the cyw43143 is a single-band, single-stream, ieee 802.11n comp liant, mac/phy/radio system-on-a-chip with internal 2.4 ghz power amplifier (pa) and integrated t/r switch. the cyw43143 suppo rts internal rx diversity by providing two antenna ports. the device enables development of usb or sdio 802.11n wlan client s that can take advantage of the high throughput and extended range of cypress second-generation solu tion. the cyw43143 maintains compatibil ity with legacy ieee 802.11b/g devices. state-of-the-art security is provided by industry standard su pport for wpa, wpa2 (802.11i) , and hardware-accelerated aes encryption/decryption, coupled with tkip, ieee 802.1x support, and a wlan authentic ation and privacy infrastructure (wapi) hardware engine. embedded hardware acceleration enables increased system perform ance and reduced host-cpu utilization in both client and access point configurations. the cyw43143 also supports cypress widely accepted and deployed wps to easily secure wlan networks. sdio and usb wireless client modu les for digital tvs, blu-ray disc ? players, set-top boxes, game consoles, and printers. supports the i 2 s digital audio interface. stand-alone wireless usb dongles and multimedia streaming boxes. cypress part numbering scheme cypress is converting the acquired iot part nu mbers from broadcom to the cypress part numbering scheme. due to this conversion, there is no change in form, fit, or functi on as a result of offering the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. features supports 3.3v 10% power supply input with high efficiency power management unit (pmu). programmable dynamic power management. eight gpios with multiplexed jtag interface. complies with usb 2.0 specification and link power management. supports standard sdio v2.0 (50 mhz, 4-bit and 1-bit) and usb host interfaces. 20 mhz reference clock. ieee 802.11x key features: ieee 802.11n compliant. 2.4 ghz internal pa. internal t/r and rx diversity switches. supports mcs 0?7 coding rates. support for short guard interval (sgi). supports usb 2.0, standard sdio v2.0 (50 mhz, 4-bit and 1-bit) host interfaces. supports the i 2 s audio interface. greenfield, mixed mode, and legacy mode support. 802.11n mpdu/msdu aggregation support for high throughput. full ieee 802.11b/g legacy comp atibility with enhanced perfor- mance. supports cypress onedriver? software. supports drivers for windows ? , linux ? , and android? operating systems. comprehensive wireless network security support that includes wpa, wpa2, and aes encryption/decryption, coupled with tkip, ieee 802.1x support, and a wapi encryption/ decryption engine. single stream ieee 802.11n su pport for 20 mhz and 40 mhz channels provides phy layer rates up to 150 mbps for typical upper-layer throughput in excess of 90 mbps. supports the ieee 802.11n rx space-time block coding (stbc) and low-density parity check (ldpc) options for improved range and power efficiency. supports an ieee 802.15.2 exter nal coexistence interface to optimize bandwidth utilization with other colocated wireless technologies such as gps, wi max, lte, bluetooth, and uwb. integrated arm cortex-m3 processor and on-chip memory for complete wlan subsystem func tionality, minimizing the need to wake up the applications processor for standard wlan functions. this allows for further minimization of power consumption while maintaining the ability to field upgrade with future features. on-chip memory includes 448 kb sram and 256 kb rom. table 1. mapping table for part number between broadcom and cypress broadcom part number cypress part number BCM43143 cyw43143 BCM43143kmlg cyw43143kmlg
document number: 002-15045 rev. *f page 2 of 44 advance cyw43143 usb 2.0 with link power management (lpm) for low power standby application. sdio out of band low power application. integrated one time programmable (otp) memory to save configuration settings. single stream ieee 802.11n su pport for 20 mhz and 40 mhz channels provides phy layer rates up to 150 mbps for typical upper-layer throughput in excess of 90 mbps. supports the ieee 802.11n rx space-time block coding (stbc) and low-density parity check (ldpc) options for improved range and power efficiency. package options: 7 mm 7 mm, 56-pin qfn package. figure 1.cyw43143 high-level block diagram iot resources cypress provides a wealth of data at http://www.cypress.co m/internet-things-iot to help you to select the right iot device for your design, and quickly and effectively integrate the device into your design. cypress provides customer access to a wide range of information, including technical documentation, schematic diagra ms, product bill of materials, pcb layout information, and soft ware updates. customers can acquire technica l documentation and soft ware from the cypress support community website ( http://community.cypress.com/ ). cyw43143 jtag gpio otp (2 ? kbits) internal ? bus serial ? flash ? interface ieee ? 802.11n ? mac ieee ? 802.11n ? phy ieee ? 802.11n 2.4 ? ghz ? radio 2.4 ? ghz pa security usb ? 2.0 ? device sdio ? or ? i 2 s ? interface flash ? memory rf ? front ? end ? (switches) sdio ? or ? i 2 s ? interface usb jtag gpio
document number: 002-15045 rev. *f page 3 of 44 advance cyw43143 contents 1. introduction ................................................................... 4 2. power management and resets .................................. 6 2.1 power management .............................................. 6 2.2 power topology .................................................... 6 2.3 reset and low-power off mode ........................... 6 3. wlan global functions .............................................. 7 3.1 gpio interface ...................................................... 7 3.2 otp ....................................................................... 7 3.3 jtag interface ...................................................... 7 3.4 crystal oscillator ................................................... 7 4. wlan usb 2.0 host interface ..................................... 8 4.1 link power management (lpm) support .............. 8 4.2 i 2 s interface .......................................................... 9 5. sdio interface ............................................................. 10 6. wireless lan mac and phy ..................................... 11 6.1 ieee 802.11n mac descripti on ............... ........... 11 6.2 ieee 802.11n phy descripti on.......... ........... ...... 12 6.3 single-band radio transcei ver........................... 13 7. pin assignments ........................................................ 14 7.1 56-pin qfn assignments.................................... 14 8. signal and pin descriptions ...................................... 18 8.1 package signal description s............................... 18 8.2 strapping options.............. .............. .............. ...... 20 9. electrical characteristics ... ........................................ 22 9.1 absolute maximum ratings ................................. 22 9.2 recommended operating conditions and dc characteristics .............................................. 22 9.3 wlan current consumptio n............................... 23 10. regulator electrical specifications ........................ 25 10.1 core buck switching regul ator......................... 25 10.2 cldo ................................................................ 25 10.3 lnldo .............................................................. 26 11. wlan specifications ............................................... 28 11.1 2.4 ghz band general rf specifications ......... 28 11.2 2.4 ghz band receiver rf specifications........ 28 11.3 2.4 ghz band transmitter rf specifications.... 29 11.4 2.4 ghz band local osci llator specifications ... 30 12. antenna specifications ............................................ 31 12.1 voltage standing wave ra tio ........................... 31 13. timing characteristics ............................................. 32 13.1 power sequence timing ................................... 32 13.2 serial flash timing......... ................................... 33 13.3 i 2 s slave mode tx timing................................. 34 13.4 sdio default mode timing ............................... 35 13.5 sdio high speed mode ti ming .............. .......... 36 13.6 usb parameters ............................................... 37 14. thermal information ................................................. 39 14.1 junction temperature estimation and psi jt versus theta jc.................................................. 39 15. package information ............ .............. .............. ........ 40 16. ordering information ................................................ 41 document history .......................................................... 42
document number: 002-15045 rev. *f page 4 of 44 advance cyw43143 1. introduction the cypress cyw43143 si ngle-chip device provides the hi ghest level of integration for wi reless systems with integrated ieee 802.11b/g/n (mac/phy/radio). it provides a sm all form-factor solution with minimal external components to drive down the cost f or mass volumes and allows for wireless media client flexibility in size, form, and function. figure 1. cyw43143 system diagram sh owing two antennas and a single stream employing a native 32-bit bus with a direct memory access (dma ) architecture, the cyw43143 offers significant performance improvements in both transfer rates and cpu utilization. flexible suppor t for a variety of system bus interfaces is provided, i ncluding usb and sdio devices. cyw43143 cyw43143 ieee ? 802.11n ? mac/phy host ? i/f ieee ? 802.11n ? 2.4 ? ghz ? radio ? transceiver ? with ? integrated ? pa rf tr ? and ? rx ? diversity ? switches ieee ? 802.11n ? mac/phy host ? i/f ieee ? 802.11n ? 2.4 ? ghz ? radio ? transceiver with ? integrated ? pa rf tr ? and ? rx ? diversity ? switches
document number: 002-15045 rev. *f page 5 of 44 advance cyw43143 figure 2 shows a block diagram of the device. figure 2. cyw43143 fu nctional block diagram power ? topology host ? interface usb20d i 2 s pmu chipcommon otp (2 ? kbits) jtag uart gpio wdog ? timer devid digital ? i/os axi ? backplane ? pl301 cldo (inside ? usb) mini ? pmu (inside ? wl ? radio) sdiod pmu ? ctrl sflash pinmux uart axi2apb ? 0 (core ? register ? ifc) saxi maxi buck (inside ? pmu) cldo (inside ? pmu) maxi saxi maxi saxi seci (bt ? coex) maxi maxi extpor_l xtal usb gsio (spi2c) jtag_sel arm cortex \ m3 jtag socsram ram (448 ? kb) rom (256 ? kb) maxi saxi rf_swctrl digital ? i/os wlan ? 802.11bgn ? (1 ? 1) ieee 802.11n mac ieee 802.11n phy ieee 802.11n 2.4 ghz radio rf ? ifc pinmux (pl368/9 ? regs. ? ifc) axi2apb ? 1 clock ? and ? reset pll (inside ? wl ? radio) dfll xtal clkrst por pll (inside ? usb) cyw43143 ipa ird itr
document number: 002-15045 rev. *f page 6 of 44 advance cyw43143 2. power management and resets 2.1 power management the cyw43143 includes an internal power management unit (pmu). the pmu takes care of powering up the chip, and also enables and disables clocks based on clock requests sent from cyw43143 internal blocks. 2.2 power topology the cyw43143 contains a high-efficiency power topology to convert input supply voltages to the s upply voltages required by the device?s internal blocks. a cbuck switching regulator is used to convert the input supply to 1.35v. internal ldos perform a low -noise conversion from 1.35v to 1.2v. as shown in figure 3 on page 6 , the cyw43143 supports two power supply configurations: a 3.3v power supply, connected to sr_vddbat5v, wrf_pa_vdd3p3, and wrf_pad_vdd3p3. a 5v power supply connected to sr_vddbat5v, wrf_pa_vdd3p3 , and wrf_pad_vdd3p3 connected to 3.3v. the latter can be obtained through a dc-dc conversion as shown in figure 3 on page 6 . the default vddio supply of the BCM43143 is 3.3v. in sdio mode, the bc m43143 supports an sdio inte rface specific voltage range of 1.8v to 3.3v. refer to pin 46 description in table 4 on page 18 . all vddio pins other than pin 46 remain at 3.3v as described in table 4 on page 18 . figure 3. power topology with the vdd33 (3.3v) main supply 2.3 reset and low-power off mode full-chip reset is achieved by switching off the 3.3v vddio volt age to pins 1, 25, 37, and 53. this puts the chip in reset and low-power off mode; in this mode the internal cbuck switcher is shut down, bri nging the total typical current consumption down to less th an 100 a. the device must be kept in reset/low-power off mode for at least 25 ms. d+ vbus d- gnd radio pa 3.3v - 5v 1.35v buck 500ma 1.35v 1.2v mini pmu 1.35v 1.2v cldo 150 ma 5v 3.3v digital core gpio sr_vddvbat5v vddio wrf_pa_vdd3p3 sr_vlx lndo_vdd1p5 lnldo_vout1p2 wrf_syn_vdd1p2 xtal_vdd1p2 vout_cldo vddc cyw43143 for 5 volts power supplies only wrf_pad_vdd3p3 2.2 h usb_avdd3p3 3.3v 2.5v ldo 50 ma usb2.0 3.3v 5v pmu bg ldo_vdd1p5 4.7 f 2.2 f 1 f 1 f 1 f
document number: 002-15045 rev. *f page 7 of 44 advance cyw43143 3. wlan global functions 3.1 gpio interface there are 19 general-purpose i/o (gpio) pins provided on the cyw43143. gpios 0?1 8 are multiplexed with the jtag, sdio, i 2 s, sflash, and serial enhanced coexistence interface (seci) functions. these pins can be used to interface to various external dev ices. upon power-up and reset, these pins become tr istated. subsequently, they can be programmed to be either input or output pins vi a the gpio control register. a programmable internal pull-up/pull-down resistor is included on each gpio. if a gpio output enable is not asserted, and the corresponding gpio signal is not being driven externally, the gpio state is determined by its programmabl e resistor. 3.2 otp the cyw43143 has 2 kbits of on-chip one-time programmable (otp ) memory that can be used for non-volatile storage of wlan information such as a mac address and other hardware-s pecific board and interface configuration parameters. 3.3 jtag interface the cyw43143 supports the ieee 1149.1 jtag boundary-scan standa rd for testing a packaged device on a manufactured board. the jtag interface is enabled by driving the jtag_sel pin high. 3.4 crystal oscillator ta b l e 2 lists the requirements fo r the crystal oscillator. figure 4 shows the recommended oscillator configuration. figure 4. recommended oscillator configuration note: the component values referenced in figure 4 are only recommended values and the correct values will have to be characterized on a per board basis. please see the refere nce board schematic for the correct characterized values. table 2. crystal oscillator requirements parameter value frequency 20 mhz mode at cut, fundamental load capacitance 16 pf esr 50 ? maximum frequency stability 10 ppm at 25c 10 ppm at 0c to +85c aging 3 ppm/year maximum the first year, 1 ppm thereafter drive level 300 w maximum q-factor 40,000 minimum shunt capacitance < 5 pf crystal 20 mhz 10 ppm 27 pf 27 pf xtal_op_in xtal_on_out 220 note: refer to reference schematics for design-specific details.
document number: 002-15045 rev. *f page 8 of 44 advance cyw43143 4. wlan usb 2.0 host interface the cyw43143 usb interface can be set to operate as a usb 2.0 port. features include the following: a usb 2.0 protocol engine th at supports the following: ? a parallel interface engine (pie) between packet buffers and usb transceiver ? up to nine endpoints, including configurable control endpoint 0 separate endpoint packet buffers with a 512-byte fifo buffer each host-to-device communication for bul k, control, and interrupt transfers configuration and status registers figure 5 shows the blocks in the device core. figure 5. wlan usb 2.0 host interface block diagram the usb 2.0 phy handles the usb protocol and the serial signalin g interface between the host and device. it is primarily respon sible for data transmission and recovery. on the transmit side, data is encoded, along with a clock, using the nrzi scheme with bit s tuffing to ensure that the receiver detects a transition in the data st ream. a sync field that precedes each packet enables the receive r to synchronize the data and clock re covery circuits. on the receive side, the serial data is deserialized, unstuffed, and checked for errors. the recovered data and clock are then shifted to the clo ck domain that is compatible with the internal bus logic. the endpoint management unit contains the pie control logic and the endpoint logic. the pie interfaces between the packet buffe rs and the usb transceiver. it handles packet identification (pid), usb packets, and transactions. the endpoint logic contains nine uniquely addressable endpoints. these endpoints are the source or sink of communication flow between the host and the device. endpoint ze ro is used as a default control port fo r both the input and output directions. the usb system software uses this default control me thod to initialize and conf igure the device info rmation and allows usb status and c ontrol access. endpoint zero is always accessible afte r a device is attached, powered, and reset. endpoints are supported by 512-by te fifo buffers, one for each in endpoint and o ne shared by all out endpoints. both tx and rx data transfers support a dma burs t of 4, which guarantees low latency and maximum throughput performance. the rx fifo can never overflow by design. the maximum usb packet size cannot be more than 512 bytes. 4.1 link power management (lpm) support the usb 2.0 host interface supports a power management feature called link power management (lpm) which is similar to the existing suspend/resume, but has transitional latencies of tens of microseconds between power states (instead of three to great er 32 \ bit ? on \ chip ? communication ? system dma ? engines rx ? fifo endpoint ? management ? unit usb ? 2.0 ? protocol ? engine usb ? 2.0 ? phy d+ d \ tx ? fifos
document number: 002-15045 rev. *f page 9 of 44 advance cyw43143 than 20 millisecond latencies of the usb 2. 0 suspend/resume). lpm simply adds a new f eature and bus state that co-exists with t he usb 2.0 defined suspend/resume. 4.2 i 2 s interface the i 2 s interface for audio supports slave mode trans mit 2.1 or 5.1 channel operation. the i 2 s signals are: i 2 s bit clock: i2s_bitclk i 2 s word select: i2s_ws i 2 s data out: i2s_sdout i2s_bitclk and i2s_ws are inputs, while i2s_sdout is an output. ch annel word lengths of 16 bits, 20 bits, 24 bits, and 32 bits are supported, and the data is justified so that the msb of the left-cha nnel data is aligned with the msb of the i 2 s bus, per the i 2 s specification. the msb of each data word is transmitted one bit clock cycle after the i2 s_ws transition, synchronous with the f alling edge of bit clock. left-channel data is transmitted when i2s_ws is low, and right-channel data is transmitted when i2s_ws is hi gh. an embedded 128 x 32 bits single port sram for data processing enhances the perf ormance of the interface. the bit depth of i 2 s is 16, 20, 24, and 32. variable sampling rates are also supported: 8k, 12k, 16k, 24k, 32k, 48k, 96k with a 12.288 mhz master clock used by the external master receiver and/or controller 22.05k, 44.1k, 88.2k with a 11.2896 mh z master clock used by the external master receiver and/or controller 96k with a 24.567 mhz master clock used by the external master receiver and/or controller the BCM43143 needs an external clock source input on the slave clock pin for the i 2 s interface. the slave clock frequency is dependent upon the audio sample rate and the external i 2 s codec.
document number: 002-15045 rev. *f page 10 of 44 advance cyw43143 5. sdio interface the sdio interface is enabled by a strapping option (see table 5 on page 21 for details). the cyw43143 supports all of the sdio version 2.0 modes: 1-bit sdio-spi mode (25 mbps) 1-bit sdio-sd mode (25 mbps) 4-bit sdio-sd default speed mode (100 mbps) 4-bit sdio-sd high speed mode (200 mbps). the sdio interface supports the full clock range from 0 to 50 mh z. the chip has the ability to stop the sdio clock between tran sactions to reduce power consumption. as an optio n, the gpio_4 or the gpio_16 pin can be mapped to provide an sdio interrupt signal. this out-of-band interrupt is hardware gener ated and is always valid (unlike the sdio in-band interrupt, which is signalled onl y when data is not driven on sdio lines ). the ability to force control of the gated clocks from within the wlan chip is also provided. three functions are supported: function 0 standard sdio function. ma ximum blocksize/bytecount = 32 bytes. function 1 backplane function to access the internal system- on-a-chip (soc) address space. maximum blocksize/ bytecount = 64 bytes. function 2 wlan function for efficient wlan packet transfer through dma. maximum blocksize/bytecount = 512 bytes.
document number: 002-15045 rev. *f page 11 of 44 advance cyw43143 6. wireless lan mac and phy 6.1 ieee 802.11n mac description the ieee 802.11n mac features include: enhanced mac for supporting 802.11n features programmable access point (ap) or station (sta) functionality programmable mode selection as independent basic service set (ibss) or infrastructure aggregated mac protocol data unit (mpdu) support for high throughput (ht) passive scanning network allocation vector (nav), inte rframe space (ifs), and timing synchr onization function (tsf) functionality rts/cts procedure support transmission of response frames (ack/cts) address filtering of receive frames as specified by ibss rules multirate support programmable target beacon transmission time (tbtt), beacon tr ansmission/cancellation, and announcement traffic indication message (atim) window coordination function (cf) conformance: setting a nav for neighborhood point coordination function (pcf) operation security through a variety of enc ryption schemes including wep, tkip, aes, wpa, wap2, and ieee 802.1x power management statistics counters for mib support the mac core supports the transmission and reception of packet sequences, together with relat ed timing, without any packet-by- packet driver interaction. time-critical tasks requiring response times of only a few milliseconds are handled in the mac core. this achieves the required medium timing while minimizing driver comp lexity. also, the mac driver processes incoming packets that ha ve been buffered in the mac core in bursts, enabling high bandwidth performance. the mac driver interacts with the mac core to prepare transmit packet queues and to analyze and forward received packets to upp er software layers. the internal blocks of the mac core are conn ected to a programmable state machine (psm) through the host interface that connects to the internal bus (see figure 6 on page 11) . figure 6. enhanced mac block diagram the host interface consists of registers for controlling and moni toring the status of the mac co re and interfacing with the tx/ rx fifos. for transmission, 32 kb of fifo buffering is available that can be dynamically allocate d to six transmit queues plus template s pace for beacons, acks, and probe responses. whenever the host has a frame to transmit, the host queues the frame into one of the transmit fifos with a tx descriptor containing tx control info rmation. the psm schedules the transmission on the medium dependi ng host ? interface ? (host ? registers) tx ? status ? fifo six ? tx ? fifos ? templates tx ? engine wireless ? security ? engine phy ? interface power ? management timing ? and ? control code ? memory programmable ? state ? machine ? (psm) data ? memory rx ? engine rx ? fifo
document number: 002-15045 rev. *f page 12 of 44 advance cyw43143 on the frame type, transmission rules in the ieee 802.11? protoc ol, and the current medium occupancy scenario. after the trans- mission completes, a tx status is returned to the host, informing the host of the transmission. the mac contains a 10 kb rx fifo. received frames are sent to th e host along with rx descriptors that contain additional frame reception information. the power management block maintains power management state informat ion of the core (and of the associated stas in the case of an ap) to help with dynamic frame transmission decisions by the core. the wireless security engine performs the r equired encryption/decryption on the tx/rx fr ames. this block supports separate tran smit and receive keys with four shared keys and 50 link-specific keys. the link-specific keys are used to establish a secure link be tween any two network nodes. the wireless security engine supports the following encryption schemes that can be selected on a per- destination basis: none: the wireless security engine acts as a pass-through wep: 40-bit secure key and 24-bit iv as defined in ieee std. 802.11-2007 wep128: 104-bit secure key and 24-bit iv tkip: ieee std. 802.11-2007 aes: ieee std. 802.11-2007 the transmit engine is responsible for the byte flow from the tx fifo to the phy interface through the encryption engine and th e addition of a crc-32 frame check sequence (fcs) as required by ieee 802.11-2007. similarly, the receive engine is responsible for byte flow from the phy interface to t he rx fifo through the decryption engine and for detection of erro rs in the rx frame. the timing block performs the tsf, nav, and ifs functionality as described in ieee std. 802.11-2007. the programmable state machine (psm) coordi nates the operation of differ ent hardware blocks required for both transmission and reception. the psm also maintains the st atistics counters required for mib support. 6.2 ieee 802.11n phy description the phy supports: programmable data rates from mcs 0?7 in 20 mhz and 40 mhz channels, as specified in 802.11n. short guard interval (sgi) and optional recept ion of two space-time block encoded streams. all scrambling, encoding, forward error corre ction, and modulation in the transmit dire ction, and inverse operations in the rec eive direction. advanced digital signal processing technology for best-in-class receive sensitivity. both mixed-mode and optional greenfield preamble of 802.11n. both long and optional short ieee 802.11b preambles. closed-loop transmit power control. per-packet receive antenna diversity. automatic gain control (agc). available per-packet channel quality and signal strength measurements. the cyw43143 phy provides baseband proc essing at all mandatory 802.11n data rates up to 150 mbps, and the legacy rates specified in ieee 802.11b/g, including 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54 mbps. this core acts as an intermediary b etween the mac and the 2.4 ghz radio, co nverting back and forth between packets and baseband waveforms.
document number: 002-15045 rev. *f page 13 of 44 advance cyw43143 figure 7. phy block diagram 6.3 single-band radio transceiver the cyw43143 has a 2.4 ghz radio transceiver that ensures lo w power consumption and robust communication in 20 mhz and 40 mhz channel bandwidths as specified in ieee 802.11n. 6.3.1 receiver path the cyw43143 has a wide dynamic range, direct conversion receiver. it employs high-order, on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band. the excellent nois e figure of the receiver makes an external lna unnecessary. 6.3.2 transmitter path baseband data is modulated and upconverted to the 2.4 ghz ism band. linear on-chip power amplifiers are included, which are capable of delivering a nominal output power exceeding +15 dbm wh ile meeting the ieee 802.11n specif ication. the tx gain has 12 8 steps of 0.25 db per step. 6.3.3 calibration the cyw43143 features dynamic on-chip calib ration, eliminating process variation acro ss components. this enables the device to be used in high-volume applications because calibration routines are not required during manufactu ring. these calibration routi nes are performed periodically in the course of normal radio operation. filters ? and ? radio ? comp frequency ? and ? timing ? synch carrier ? sense, ? agc, ? and ? rx ? fsm radio ? control ? block common ? logic ? block filters ? and ? radio ? comp afe ? and ? radio mac ? interface buffers ofdm ? demodulate viterbi decoder tx ? fsm pa ? comp modulation ? and ? coding frame ? and ? scramble fft/ifft cck/dsss ? demodulate descramble ? and ? deframe coex modulate ? and ? spread
document number: 002-15045 rev. *f page 14 of 44 advance cyw43143 7. pin assignments 7.1 56-pin qfn assignments the 56-pin qfn package pin assignments are shown in figure 8 . figure 8. cyw43143 56-pin qfn package 7.1.1 56-pin qfn signals pin assignments by pin number table 3. pin assignments by pin number pin signal name 1vddio 2uart_rx 3uart_tx 4 wrf_pad_vdd3p3 5gnd 6 wrf_pa_vdd3p3 1 2 3 4 5 6 7 56 55 54 53 52 51 50 49 48 47 46 45 44 43 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 32 31 30 29 33 15 16 17 18 19 20 21 22 23 24 25 26 27 28 vddio uart_rx uart_tx wrf_pad_vdd3p3 nc wrf_pa_vdd3p3 wrf_out_in1 nc wrf_rfin2 wrf_gpioout lnldo_vdd1p5 lnldo_vdd1p5 lnldo_vdd1p5 lnldo_vdd1p5 usb_rref usb_monpll usb_avdd3p3 usb_dm usb_dp vddio sflash_so|gsio_sdo sflash_clk|gsio_sclk sflash_si|gsio_sdi vddc vout_cldo sr_vlx ldo_vdd1p5 sr_vddbat5v l n l d o _ v o u t 1 p 2 w r f _ s y n _ v d d 1 p 2 x t a l _ o p _ i n x t a l _ o n _ o u t j t a g _ s e l v d d c g p i o 0 g p i o 1 g p i o 2 v d d i o g p i o 3 g p i o 4 g p i o 5 x t a l _ v d d 1 p 2 v d d c g p i o 1 8 g p i o 1 7 v d d i o g s i o _ c s n s f l a s h _ c s n s d i o _ d a t a 0 s d i o _ d a t a 1 s d i o _ c l k s d i o _ c m d s d i o _ d a t a 2 s d i o _ d a t a 3 v d d i o v d d c BCM43143 7 ? x ? 7 ? qfn
document number: 002-15045 rev. *f page 15 of 44 advance cyw43143 7 wrf_out_in1 8gnd 9 wrf_rfin2 10 wrf_gpioout 11 lnldo_vdd1p5 12 lnldo_vdd1p5 13 lnldo_vdd1p5 14 lnldo_vdd1p5 15 lnldo_vout1p2 16 wrf_syn_vdd1p2 17 xtal_vdd1p2 18 xtal_op_in 19 xtal_on_out 20 jtag_sel 21 vddc 22 gpio0 23 gpio1 24 gpio2 25 vddio 26 gpio3 27 gpio4 28 gpio5 29 sr_vlx 30 sr_vddbat5v 31 vout_cldo 32 ldo_vdd1p5 33 vddc 34 sflash_si|gsio_sdi 35 sflash_clk|gsio_sclk 36 sflash_so|gsio_sdo 37 vddio 38 usb_dp 39 usb_dm 40 usb_avdd3p3 41 usb_monpll 42 usb_rref 43 vddc 44 sdio_data3 45 sdio_data2 46 vddio 47 sdio_cmd pin signal name
document number: 002-15045 rev. *f page 16 of 44 advance cyw43143 48 sdio_clk 49 sdio_data1 50 sdio_data0 51 sflash_csn 52 gsio_csn 53 vddio 54 gpio17 55 gpio18 56 vddc pin signal name
document number: 002-15045 rev. *f page 17 of 44 advance cyw43143 pin assignments by pin name table 4. pin assignments by signal name signal name pin gpio0 22 gpio1 23 gpio2 24 gpio3 26 gpio4 27 gpio5 28 gpio17 54 gpio18 55 gsio_csn 52 jtag_sel 20 ldo_vdd1p5 32 lnldo_vdd1p5 11 lnldo_vdd1p5 12 lnldo_vdd1p5 13 lnldo_vdd1p5 14 lnldo_vout1p2 15 gnd 5 gnd 8 sdio_clk 48 sdio_cmd 47 sdio_data0 50 sdio_data1 49 sdio_data2 45 sdio_data3 44 sflash_clk|gsio_sclk 35 sflash_csn 51 sflash_si|gsio_sdi 34 sflash_so|gsio_sdo 36 sr_vddbat5v 30 sr_vlx 29 uart_rx 2 uart_tx 3 usb_avdd3p3 40 usb_dm 39 usb_dp 38 usb_monpll 41 usb_rref 42 vddc 21 vddc 33 vddc 43 vddc 56 vddio 1 vddio 25 vddio 37 vddio 46 vddio 53 vout_cldo 31 wrf_gpioout 10 wrf_out_in1 7 wrf_pa_vdd3p3 6 wrf_pad_vdd3p3 4 wrf_rfin2 9 wrf_syn_vdd1p2 16 xtal_on_out 19 xtal_op_in 18 xtal_vdd1p2 17 signal name pin
document number: 002-15045 rev. *f page 18 of 44 advance cyw43143 8. signal and pin descriptions 8.1 package signal descriptions the signal name, type, and description of each pin in the cyw43143 56-pin qfn package is listed in ta b l e 4 . the symbols shown in the type column indicate pin directions (i /o = bidirectional, i = input, o = output, and od = open drain output) and the intern al pull- up/pull-down characteristics (pu = weak internal pull-up resistor and pd = weak internal pull-down resistor), if any. resistor s trapping options are defined in table 5 on page 21 . table 4. cyw43143 signal descriptions pin signal type description sdio bus interface 48 sdio_clk i/o sdio clock when not used as sdio this is a gener al purpose gpio pin (gpio12) or an i 2 s audio interface signal (i2s_ws) 47 sdio_cmd i/o sdio bus command line when not used as sdio this is a general purpose gpio pin (gpio11) or an i 2 s audio interface signal (i2s_bitclk) 50 sdio_data0 i/o sdio data line 0 when not used as sdio this is a general purpose gpio pin (gpio14) 49 sdio_data1 i/o sdio data line 1 when not used as sdio this is a gener al purpose gpio pin (gpio13) or an i 2 s audio interface signal (i2s_sdout) 45 sdio_data2 i/o sdio data line 2 when not used as sdio this is a general purpose gpio pin (gpio10) 44 sdio_data3 i/o sdio data line 3 when not used as sdio this is a general purpose gpio pin (gpio9) usb interface 39 usb_dm i/o usb data negative 38 usb_dp i/o usb data positive 41 usb_monpll ? usb reserved pin for diagnostic purposes only 42 usb_rref ? usb bandgap reference resistor/capac itor, tie this pin in parallel through a 100 pf capacitor and a 4 k ? resistor to ground wlan rf signal interface 7 wrf_out_in1 i/o 2.4 ghz rf output, 2.4 ghz rf input 1 9 wrf_rfin2 i 2.4 ghz rf input 2 10 wrf_gpioout o wlan reference output. connect to ground through a 15 k ? , 1% resistor. i 2 s audio interface 47 i2s_bitclk i/o i 2 s serial bit clock, only available when no sdio i/f 48 i2s_ws i/o i 2 s word select, only available when no sdio i/f 49 i2s_sdout i/o i 2 s serial data out, only available when no sdio i/f serial flash interface and spi/bsc interface 51 sflash_csn i/o serial flash chip select. when not used as sflash, this is a general purpose gpio pin (gpio15) 34 sflash_si gsio_sdi i/o this pin is muxed with: ? serial flash data in ? spi/bsc data in when not used as sflash or gsio this is a general purpose gpio pin (gpio6)
document number: 002-15045 rev. *f page 19 of 44 advance cyw43143 36 sflash_so gsio_sdo i/o this pin is muxed with: ? serial flash data out ? spi/bsc data out when not used as sflash or gsio this is a general purpose gpio pin (gpio8) 35 sflash_clk gsio_sclk i/o this pin is muxed with: ? serial flash clock ? spi/bsc clock when not used as sflash or gsio this is a general purpose gpio pin (gpio7) 52 gsio_csn i/o spi/bsc chip select. when not used as gsio this is a general purpose gpio pin (gpio16). gpio pins 22 gpio0 tdi btcx_rf_active seci_in0 i/o this pin is muxed with: ? gpio0, a general purpose i/o pin ? jtag test data in ? legacy bt coexistence rf active ? seci in0 23 gpio1 tdo btcx_tx_conf seci_out i/o this pin is muxed with: ? gpio1, a general purpose i/o pin ? jtag test data out ? legacy bt coexistence tx conf ? seci out 24 gpio2 tck btcx_status seci_aux0 i/o this pin is muxed with: ? gpio2, a general purpose i/o pin ? jtag test clock ? legacy bt coexistence status ? seci aux0 26 gpio3 trst-l btcx_prisel seci_in1 i/o this pin is muxed with: ? gpio3, a general purpose i/o pin ? jtag test reset low ? legacy bt coexistence priority select ? seci in1 27 gpio4 tms btcx_freq i/o this pin is muxed with: ? gpio4, a general purpose i/o pin ? jtag test mode select ? legacy bt coexistence freq 28 gpio5 extpor_l i/o (pu) this pin is muxed with: ? gpio5, a general purpose i/o pin ? external power-on reset low, when jtag_sel high 54 gpio17 i/o (pd) general purpose i/o pin 55 gpio18 i/o (pd) general purpose i/o pin table 4. cyw43143 signal descriptions (cont.) pin signal type description
document number: 002-15045 rev. *f page 20 of 44 advance cyw43143 8.2 strapping options the pins listed in ta b l e 5 are sampled at power-on reset (por) to determine the various operating modes. sampling occurs within a few milliseconds following internal por or deassertion of exte rnal por. after por, each pin assumes the function specified in the signal descriptions table. each pin has an internal pull-up (p u) or pull-down (pd) resistor t hat determines the default mode. t o change the mode, connect an external pu resistor to vddio or a pd resistor to gnd (use 10 k ? or less) 1 . uart interface 2 uart_rx i/o (pd) uart receive data (sw debug) 3 uart_tx i/o (pu) uart transmit data (sw debug) crystal oscillator 19 xtal_on_out o xtal oscillator output. connect a 20 mhz, 10 ppm crystal between the xtal_on_out and xtal_op_in pins 18 xtal_op_in i xtal oscillator input test pins 20 jtag_sel i (pd) jtag select strap pins 2 uart_rx i/o (pd) strap remaptorom[1] 3 uart_tx i/o (pu) strap remaptorom[0] 34 sflash_si i/o (pd) strap sdiohighdrive 54 gpio17 i/o (pd) strap sdioenabled 55 gpio18 i/o (pd) strap sdioiso integrated voltage regulators 11, 12, 13, 14 lnldo_vdd1p5 pwr lnldo 1.5v input 15 lnldo_vout1p2 pwr lnldo 1.2v output 30 sr_vddbat5v pwr vbat power input 29 sr_vlx pwr cbuck switching regulator output 31 vout_cldo pwr output of core ldo 32 ldo_vdd1p5 pwr input of core ldo wlan power supplies 40 usb_avdd3p3 pwr usb 3.3v input 16 wrf_syn_vdd1p2 pwr rf synthesizer vdd 1.2v input 6 wrf_pa_vdd3p3 pwr wlan pa 3.3v supply 4 wrf_pad_vdd3p3 pwr wlan pa driver 3.3v supply 17 xtal_vdd1p2 pwr xtal oscillator 1.2v supply miscellaneous power supplies and ground 21, 33, 43, 56 vddc pwr core supply for wlan 1, 25, 37, 53 vddio pwr i/o supply for pads (3.3v) 46 vddio pwr i/o supply for sdio pads (1.8v to 3. 3v). can only be 3.3v when usb is used. h gnd_slug gnd ground 5, 8 gnd gnd ground 1. cyw43143 reference board schematics can be obta ined through your cypresscypress representative. table 4. cyw43143 signal descriptions (cont.) pin signal type description
document number: 002-15045 rev. *f page 21 of 44 advance cyw43143 table 5. strapping options signal name mode default description [uart_rx, uart_tx] remaptorom[1:0] [pd,pu] 00 = boot from sram , armcm3 in reset, no sflash connected 01 = boot from rom, no sflash connected (default) 10 = boot from sflash 11 = invalid gpio17 sdioenabled pd 0 = usb enabled, sdio pins can be gpio or i 2 s (default) 1 = sdio enabled gpio18 sdioiso pd 0 = sdio pads are not in isolation mode (default) 1 = keep sdio pads in isolation mode sflash_si sdiohighdrive pd 0 = sdio pins drive strengt h set by sdiod core or pmu chip control (= default) 1 = sdio pins drive strength set by sdio d core to either 12 ma or 16 ma
document number: 002-15045 rev. *f page 22 of 44 advance cyw43143 9. electrical characteristics note: values in this data sheet are design goals and are subject to change based on the results of device characterization. 9.1 absolute maximum ratings caution! these specifications indicate levels where permanent damage to the device can occur. functional operation is not guaranteed under these conditions. operation at absolute maximum conditions for extended periods can adversely affect the long-ter m reliability of the device. 9.2 recommended operating conditions and dc characteristics table 6. absolute maximum ratings rating symbol minimum maximum unit dc supply for cbuck switching regulator sr_vddbat5v ?0.5 5.5 v dc supply voltage for the wl pa/pa driver wrf_pa_vdd3p3, wrf_pad_vdd3p3 ?0.5 3.8 v dc supply voltage for i/o vddio ?0.5 3.8 v dc supply voltage for the cyw43143 core vddc ?0.5 1.32 v dc supply voltage for cyw43143 rf blocks wrf_syn_vdd1p2, xtal_vdd1p2 ?0.5 1.32 v dc input supply voltage for cldo and lnldo ldo_vdd1p5, lnldo_- vdd1p5 ?0.5 2.1 v maximum junction temperature t j_max ?125c operating humidity ? ? 85 % ambient operating temperature ? ? 65 a a. on a 1s1p jedec board, not exceeding t j_max , see section 14.: ?thermal information,? on page 39 . c storage temperature t stg ?40 125 c storage humidity ? ? 60 % esd protection (hbm) v esd ? 2000 v table 7. guaranteed operating conditions and dc characteristics element parameter value unit minimum typical maximum dc supply for cbuck switching regulator sr_vddbat5v 2.3 3.6 5.25 v dc supply voltage for wl pa/pa driver wrf_pa_vdd3p3, wrf_pad_vdd3p3 2.97 3.3 3.63 v dc supply voltage for core vddc 1.14 1.2 1.26 v dc supply voltage for rf blocks in chip vddrf 1.14 1.2 1.26 v sdio interface i/o pins a input high voltage vih 0.625 vddio ? ? v input low voltage vil ? ? 0.25 vddio v output high voltage @ 2 ma voh 0.75 vddio ? ? v output low voltage @ 2 ma vol ? ? 0.125 vddio v other digital i/o pins input low voltage vil ? ? 0.8 v
document number: 002-15045 rev. *f page 23 of 44 advance cyw43143 9.3 wlan current consumption the wlan current consumption measurements are shown in ta b l e 8 through table 9 on page 24 . input high voltage vih 2.0 ? ? v output low voltage @ 2 ma vol ? ? 0.4 v output high voltage @ 2 ma voh vddio ? 0.4v ? ? v rf switch control i/o pins input low voltage vil ? ? 0.8 v input high voltage vih 2.0 ? ? v output low voltage @ 2 ma vol ? ? 0.4 v output high voltage @ 2 ma voh vddio ? 0.4v ? ? v input capacitance cin ? ? 5 pf a. vddio voltage tolerance is 10%; for sdio 1.8v levels (vddio at pin 46 = 1.8v 10%), the maximum sdio cl ock frequency should be limited to 25 mhz in high-speed mode only. table 8. wlan current consumption in sdio mode using sr_vddbat5v a a. typical numbers, measured at 3.3v, 25c. host interface sdio vddio sr_vddbat5v wrf_pa_vdd3p3 wrf_pad_vdd3p3 usb_avdd3p3 i_total p_total ma mw off (low power off mode: vddio switched off) 0 0.07 0 0 0 0.07 0.2 sleep b b. inter-beacon sleep. 12011< 5< 17 power save c c. beacon interval = 102.4 ms, dtim = 3, beacon duration = 1 ms @ 1 mbps. integrated sleep + wake up + beacon rx current over 3 dtim intervals. 13011< 6< 20 rx (listen), 2.4 ghz ht 20 d d. carrier sense (cca) when no carrier present. 1 40 0 1 0 42 139 rx (active), 2.4 ghz ht 20 e,f e. carrier sense (cs) detect/packet rx. f. applicable to all supported rates. 2 65 0 1 0 68 224 tx cck (20 dbm @ chip port, 2.4 ghz ht 20) g g. duty cycle is 100%. 1 56 329 30 0 416 1373 tx ofdm, 54 mbps (?20 dbm @ chip port, 2.4 ghz ht 20) g 2 58 295 30 0 385 1265 tx mcs7 (18 dbm @ chip port, 2.4 ghz ht20) g 2 72 249 24 0 347 1145 tx mcs7 (18 dbm @ chip port, 2.4 ghz ht40) g 2 78 272 25 0 377 1244 table 7. guaranteed operating conditions and dc characteristics (cont.) element parameter value unit minimum typical maximum
document number: 002-15045 rev. *f page 24 of 44 advance cyw43143 table 9. wlan current consumpt ion in usb mode using vdd33 a a. typical numbers, measured at 3.3v, 25c. host interface usb vddio sr_vddbat5v wrf_pa_vdd3p3 wrf_pad_vdd3p3 usb_avdd3p3 i_total p_total ma mw off (low power off mode: vddio switched off) 0 0.07 0 0 0 0.07 0.2 sleep b b. inter-beacon sleep. 0.4 2 0 1 5.6 < 9 < 30 power save c c. beacon interval = 102.4 ms, dtim = 3, beacon duration = 1 ms @ 1 mbps. integrated sleep + wake up + beacon rx current over 3 dtim intervals. 0.4 3 0 1 5.6 < 10 < 33 rx (listen), 2.4 ghz ht 20 d d. carrier sense (cca) when no carrier present. 0.4 45 0 1 22 68 226 rx (active), 2.4 ghz ht 20 e,f e. carrier sense (cs) detect/packet rx. f. applicable to all supported rates. 0.4 70 0 1 23 94 312 tx cck (20 dbm @ chip port, 2.4 ghz ht 20) g g. duty cycle is 100%. 0.5 55 320 30 21 427 1407 tx ofdm, 54 mbps (?20 dbm @ chip port, 2.4 ghz ht 20) g 0.4 59 265 30 21 376 1239 tx mcs7 (18 dbm @ chip port, 2.4 ghz ht20) g 0.6 74 248 24 21 368 1213 tx mcs7 (18 dbm @ chip port, 2.4 ghz ht40) g 1.6 80 272 25 21 400 1319
document number: 002-15045 rev. *f page 25 of 44 advance cyw43143 10. regulator elect rical specifications note: values in this data sheet are design goals and are subject to change based on the results of device characterization. functional operation is not guarant eed outside of the specification limits provided in this section. 10.1 core buck switching regulator table 10. core buck switching regulator (cbuck) specifications specification notes min typ max units input supply voltage (dc) dc voltage ran ge inclusive of disturbances. 2.3 3.6 5.25 v input supply voltage (spikes) up to 10 seconds cumulative duration over 7 years lifetime. 10 ms maximum pulse width. ??5.5v pwm mode switching frequency ccm: load > 100 ma sr_vddbat5v = 3.6v 246mhz pwm output current ? ? ? 500 a a. 500 ma tt junction temp 110c. derate to 372 ma for t j > 125c. ma output current limit ? ? 1390 ? ma output voltage range programmable, 30 mv steps default = 1.35v 1.2 1.35 1.5 v pwm output voltage dc accuracy includes load and line regulation. forced pwm mode ?4 ? 4 % pwm ripple voltage, static measur e with 20 mhz bandwidth limit. ? 7 20 mvpp pwm mode peak efficiency peak efficiency at 200 ma load 78 84 ? % pfm mode efficiency 5 ma load current ? 65 ? % low power operating mode (lpom) efficiency 5 ma load current ? 80 ? % start-up time from power down vddio already on and steady. time from reg_on rising edge to cldo reaching 1.2v ??850s external inductor 0603 size, 30%, 0.26 25% ohms 1.2 2.2 3.3 h external output capacit or ceramic, x5r, 0402, esr <30m ? at 4 mhz, 20%, 6.3v 2.53 b b. minimum capacitor value refers to the re sidual capacitor value after taking into ac count the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 10 f external input capacitor for sr_vddbatp5v pin, ceramic, x5r, 0603, esr < 30 m ? at 4 mhz, 20%, 6.3v, 4.7 f 0.76 b 4.7 ? f operating junction temperature ? ?40 50 125 c input supply voltage ramp-up time 0 to 4.3v 40 ? ? s
document number: 002-15045 rev. *f page 26 of 44 advance cyw43143 10.2 cldo 10.3 lnldo table 11. cldo specifications specification notes min typ max units input supply voltage (v in ) min = 1.2 + 0.1v = 1.3v dropout voltage requireme nt must be met under maximum load. 1.2 1.35 1.5 v output current a a. output current is measured at 125c junction temperature. ? ??150ma output voltage (v o ) programmable in 25 mv steps. default = 1.2v 1.1 1.2 1.275 v dropout voltage at max load ? ? 100 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 10 ? a line regulation v in from (v o + 0.1v) to 1.5v, maximum load ? ? +1.1 %v o /v load regulation load from 1 ma to 150 ma ? ? 0.02 %v o /ma leakage current b b. leakage current is measured by 85c junction temperature. power-down ? ? 10 a power supply rejection ratio (psrr) @1 khz vin 1.35v c o = 2.2 f 20 ? ? db pmu start-up time sr_vddbat5v up and stable. time from the vddio rising edge to the cldo reaching 1.2v. ? ? 850 s ldo turn-on time ldo turn-on time when rest of the chip is up ? ? 180 s in-rush current during turn-on measured when the output capacitor is fully discharged. ??150ma external output capacitor, c o total esr: 30?200 m ? 1.67 c c. minimum capacitor value refers to the re sidual capacitor value after taking into ac count the part-to-part tolerance, dc-bias, temperature, and aging. 1?f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. total esr (trace/capacitor): 30 m ? ?200 m ? ?12.2f operating temperature junct ion temperature ?40 50 125 c table 12. lnldo specifications specification notes min typ max units input supply voltage (v in ) min = 1.2v o + 0.1v = 1.3v dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? ? ? 100 ma output voltage (v o ) programmable in 25 mv steps. default = 1.2v 1.1 1.2 1.275 v dropout voltage at maximum load ? ? 100 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ? 44 ? a line regulation v in from (v o + 0.1v) to 1.5v, maximum load ?0.3 ? +0.3 %v o /v
document number: 002-15045 rev. *f page 27 of 44 advance cyw43143 load regulation load from 1 ma to 300 ma ? 0.02 0.05 %v o /ma transient undershoot ? ? ? tbd mv transient overshoot ? ? ? tbd mv leakage current power-down ? ? 10 a output noise @30 khz, 60 ma load c o = 1 f @100 khz, 60 ma load c o = 1 f ? ? 60 30 nv/rt hz nv/rt hz psrr @ 1khz, input > 1.3v, c o = 1 f, v o = 1.2v 20 ? ? db pmu start-up time from power-down ? ? 850 s ldo turn-on time ldo turn-on time when rest of chip is up ? ? 180 s in-rush current during turn-on measured when the output capacitor is fully discharged. ? ? 150 ma external output capacitor (c o ) total esr (trace/capacitor): 30 m ? ?200 m ? 0.74 a 12.2f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. total esr (trace/capacitor): 30 m ? ?200 m ? ? 1 2.2 f operating temperature juncti on temperature ?40 50 125 c a. minimum capacitor value refers to the re sidual capacitor value after taking into ac count the part-to-part tolerance, dc-bias, temperature, and aging. table 12. lnldo specifications specification notes min typ max units
document number: 002-15045 rev. *f page 28 of 44 advance cyw43143 11. wlan specifications note: values in this data sheet are design goals and are subject to change based on the results of device characterization. 11.1 2.4 ghz band general rf specifications 11.2 2.4 ghz band receiver rf specifications the receiver specifications in cluding sensitivity are shown in ta b l e 1 4 and table 15 on page 28 . table 13. 2.4 ghz band general rf specifications item condition minimum typical maximum unit tx/rx switch time including tx ramp down ? 5 10 s rx/tx switch time including tx ramp up ? 5 5 s table 14. 2.4 ghz band receiver rf specifications characteristic condition minimum typical maximum unit cascaded noise figure ? ? 4 ? db maximum receive level a a. when using a suitable external rf switch. @ 1, 2 mbps ?4 ? ? dbm @ 5.5, 11 mbps ?10 ? ? dbm @ 54 mbps ?10 ? ? dbm adjacent channel power rejection ? dsss at 11 mbps b b. difference between interfering and desired signal (>25 mhz apart) at 8% per for 1024-octet physic al-layer service data units (psdus) with desired signal level as specified. rx = ?70 dbm 35 ? ? db return loss zo = 50 ? , across dynamic range tbd tbd tbd db maximum receiver gain ? ? >90 ? db table 15. 2.4 ghz receiver sensitivity rate/modulation typical receive sensitivity a b (dbm) 1 mbps dsss ?97 2 mbps dsss ?95 5.5 mbps cck ?91 11 mbps cck ?89 6 mbps ofdm ?91 9 mbps ofdm ?90 12 mbps ofdm ?88 18 mbps ofdm ?86 24 mbps ofdm ?84 36 mbps ofdm ?81 48 mbps ofdm ?78 54 mbps ofdm ?76 mcs0 (20 mhz channel) ?91 mcs1 (20 mhz channel) ?88
document number: 002-15045 rev. *f page 29 of 44 advance cyw43143 11.3 2.4 ghz band transmitter rf specifications mcs2 (20 mhz channel) ?86 mcs3 (20 mhz channel) ?83 mcs4 (20 mhz channel) ?81 mcs5 (20 mhz channel) ?77 mcs6 (20 mhz channel) ?75 mcs7 (20 mhz channel) ?73 mcs0 (40 mhz channel) ?90 mcs1 (40 mhz channel) ?86 mcs2 (40 mhz channel) ?84 mcs3 (40 mhz channel) ?82 mcs4 (40 mhz channel) ?78 mcs5 (40 mhz channel) ?74 mcs6 (40 mhz channel) ?72 mcs7 (40 mhz channel) ?70 a. values are measured at the input of the cyw43143. thus, they include insertion losses from the integrated baluns and integrat ed t/r switches, but exclude losses from the exter nal circuits. for the 1, 2, 5.5, and 11 m bps rates, sensitivity is defined as an 8% packet error rate (per) for 1000-octet psdus. for 11g rates (6 mbps ofdm up to 54 mbps ofdm), sensitivity is defined as a 10% packet error rate (pe r) for 1000-octet psdus. for 11n rates (mcs0 to mcs7), sensit ivity numbers are provide for 10% per and 4000byte packets. b. sensitivity levels at vcc=3.3v6%; at vc c=3.3 10%, sensitivity levels may be degraded. table 16. 2.4 ghz band transmitter rf specifications characteristic condition min. typ. max. unit rf output frequency range ? 2400 ? 2500 mhz chip output power a (evm and acpr compliant, vcc=3.3v 6% b ) 20 mhz channel dsss/cck rates 1, 2, 5.5, and 11 mbit/s ?? 21.0 dbm 802.11g rates 6, 9, 12, 18, 24, and 36 mpps ?? 20.0 802.11g rate 48 mbps ?? 19.0 802.11g rate 56 mbps ?? 18.0 ofdm rates mcs0-mcs5 ?? 20.0 ofdm rate mcs6 ?? 19.0 ofdm rate mcs7 ?? 18.0 40 mhz channel ofdm rates mcs0- mcs4 ?? 19.5 ofdm rate mcs5 ?? 19.0 ofdm rate mcs6 ?? 18.0 ofdm rate mcs7 ?? 17.0 table 15. 2.4 ghz receiver sensitivity rate/modulation typical receive sensitivity a b (dbm)
document number: 002-15045 rev. *f page 30 of 44 advance cyw43143 11.4 2.4 ghz band local oscillator specifications gain flatness maximum gain ? ? 2 db output ip3 maximum gain ? 37 ? dbm output p1db ? ? 27 ? dbm carrier suppression ? 15 ? ? dbr cck tx spectrum mask @ maximum gain fc ?22 mhz < f < fc ?11 mhz ? ? ?30 dbr fc +11 mhz < f< fc +22 mhz ? ? ?30 dbr f < fc ?22 mhz; and f > fc +22 mhz ? ? ?50 dbr ofdm tx spectrum mask (chip output power = 16 dbm) f < fc ?11 mhz and f > fc +11 mhz ? ? ?26 dbc f < fc ?20 mhz and f > fc +20 mhz ? ? ?35 dbr f < fc ?30 mhz and f > fc +30 mhz ? ? ?40 dbr tx modulation accuracy (i.e. evm) at maximum gain ieee 802.11b mode ? ? 35% ? ieee 802.11g mode qam64 54 mbps ? ? 5% ? gain control step size ? ? 0.25 ? db/step amplitude balance c dc input ?1 ? 1 db phase balance dc input ?1.5 ? 1.5 baseband differential input voltage shaped pulse ? 0.6 ? vpp tx power ramp up 90% of final power ? ? 2 ? sec tx power ramp down 10% of final power ? ? 2 ? sec a. power control will back off output power by 1. 5 db ensuring evm and acpr limits are always met. b. linear output power at 3.3v 10% supply voltage may be degraded and evm/acpr compliant output power may be lower than listed. c. at a 3 mhz offset from the carrier frequency. table 17. 2.4 ghz band local oscillator specifications characteristic condition minimum typical maximum unit vco frequency range ? 2412 ? 2484 mhz reference input frequency range ? ? various a a. reference supported frequencies range from 12 mhz to 52 mhz. ?mhz reference spurs ? ? ? ?34 dbc local oscillator phase noise, single-sided from 1? 300 khz offset ????86.5dbc/hz clock frequency tolerance ? ? ? 20 ppm table 16. 2.4 ghz band transmitter rf specifications (cont.) characteristic condition min. typ. max. unit
document number: 002-15045 rev. *f page 31 of 44 advance cyw43143 12. antenna specifications 12.1 voltage standing wave ratio the voltage standing wave ratio (vswr) into the antenna should be less than 2.5:1.
document number: 002-15045 rev. *f page 32 of 44 advance cyw43143 13. timing characteristics 13.1 power sequence timing the recommended power-up sequence is to bring up the power supp lies in the order of the rated voltage. this power-up sequence minimizes the possibility of a latchup condition. in the case of a 3.3v supply (see figure 1 ), the 3.3v supplied to sr_vddbat5v, wrf_pa_vdd3p3, wrf_pad_vdd3p3, usb_a- vdd3p3, and vddio can ramp at the same time. in the case of a 5v supply (see figure 2 on page 32 ), the 5v first ramps on sr_vddbat5v, foll owed by bring- up of the 3.3v supply to wrf_pa_vdd3p3, wrf_pad_vdd3p3, usb_avdd3p3, and vddio. the power-up timing parameters for both configurations are shown in table 18 on page 33 . figure 1. power-up se quence timing?3v supply figure 2. power-up sequence timing?5v supply with external dc-dc conversion vddio sr_vddbat5v interface sr_vlx vddc t 2 wrf_pa(d)_vdd3p3 BCM43143 ? tri \ state internal ? reset t 3 usb_avdd3p3 vddio sr_vddbat5v interface sr_vlx vddc t 2 wrf_pa(d)_vdd3p3 t 1 43143 ? tri \ state internal ? reset t 3 usb_avdd3p3
document number: 002-15045 rev. *f page 33 of 44 advance cyw43143 13.2 serial flash timing figure 3. serial flash timing diag ram (stmicroelectronics-compatible) table 18. power-up timing parameters symbol description minimum typical maximum unit t 1 sr_vddbat5v to 3p3 active 0 a a. in the case of the 3.3v power supply, t1 = 0 for sr_vddbat5v, wrf_pa_vdd3p3, and wrf_pad_vdd3p3. 50 b b. in the case of the 5v power supply, sr_vdd_bat5v is di rectly connected to 5v, but the connection to wrf_pa_vdd3p3, wrf_pad_vdd3p3, and vddio must be made through a dc-dc converter chip to convert 5v to 3v3. since the converter chip introduces a delay in the ramp-up time, t1 = 50 s (nominal). the actual va lue of t1 will vary slightly based on the particular dc-dc conve rter chip used in the design. ?s t 2 time from vddio rising edge to vddc reaching 1.2v ? ? 850 s t 3 time from vddc reaching 1.2v to internal reset deactivation 30 35 50 ms table 19. serial flash timing parameter descriptions minimum typical maximum units f sck serial flash clock frequency ? 12.5 49.2 mhz t wh serial flash clock high time 9 ? ? ns t wl serial flash clock low time 9 ? ? ns t r , t f a clock rise and fall times b tbd ? ? v/ns t css chip select active setup time 5 ? ? ns t cs chip select deselect time 100 ? ? ns t csh chip select hold time 5 ? ? ns t su data input setup time 2 ? ? ns t h data input hold time 5 ? ? ns t ho data output hold time 0 ? ? ns t v clock low to output valid ? ? 8 ns sflash_csn sflash_clk sflash_si sflash_so high impedance high impedance t css t wl t wh t csh t cs t f t ho t v t h t su valid on valid in t r
document number: 002-15045 rev. *f page 34 of 44 advance cyw43143 13.3 i 2 s slave mode tx timing in i 2 s slave mode, the serial clock (i2s_bitclk) input speed can vary up to a maximum of 12.288 mhz. i 2 s slave mode timing is illustrated in figure 4 . figure 4. i 2 s slave mode timing a. t r and t f are expressed as a slew-rate. b. peak-to-peak table 20. timing for i 2 s transmitters and receivers parameter transmitter receiver lower limit upper limit lower limit min max min max min max clock period t t tr t tr slave mode: clock accepted by transmitter or receiver: high t hc low t lc rise time t rc 0.35 t r 0.35 t r 0.15 t tr 0.35 t r 0.35 t r transmitter: delay t dtr hold time t htr 0 0.8 t bitclk ws sd msb lsb msb word n ? 1 right channel word n left channel word n + 1 right channel t = clock period ttr = minimum allowed clock period for transmitter t t lc = ? 0.35t v h = 2.0v v l = 0.8v t hc = ? 0.35t sd/ws t htr = ? 0 t dtr = ? 0.8t t rc t > ttr bitclk
document number: 002-15045 rev. *f page 35 of 44 advance cyw43143 13.4 sdio default mode timing sdio default mode timing is shown by the combination of figure 5 and ta b l e 2 1 . figure 5. sdio bus timing (default mode) receiver: setup time t sr hold time t hr 0.2 t r 0 table 21. sdio bus timing a parameters (default mode) parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) frequency ? data transfer mode fpp 0 ? 25 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl 10 ? ? ns clock high time twh 10 ? ? ns clock rise time ttlh ? ? 10 ns clock low time tthl ? ? 10 ns inputs: cmd, dat (referenced to clk) input setup time tisu 5 ? ? ns input hold time tih 5 ? ? ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly 0 ? 14 ns output delay time ? identification mode todly 0 ? 50 ns table 20. timing for i 2 s transmitters and receivers parameter transmitter receiver lower limit upper limit lower limit min max min max min max t wl t wh f pp t thl t isu t tlh t ih t odly (max) t odly (min) input output sdio_clk
document number: 002-15045 rev. *f page 36 of 44 advance cyw43143 13.5 sdio high speed mode timing sdio high-speed mode timing is shown by the combination of figure 6 and table 22 on page 36 . figure 6. sdio bus timing (high-speed mode) a. timing is based on cl 40 pf load on cmd and data. b. min(vih) = 0.7 vddio_sd and max(vil) = 0.2 vddio_sd. table 22. sdio bus timing a parameters (high-speed mode) parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) frequency ? data transfer mode fpp 0 ? 50 c mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl 7 ? ? ns clock high time twh 7 ? ? ns clock rise time ttlh ? ? 3 ns clock low time tthl ? ? 3 ns inputs: cmd, dat (referenced to clk) input setup time tisu 6 ? ? ns input hold time tih 2 ? ? ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly ? ? 14 ns output hold time toh 2.5 ? ? ns total system capacitance (each line) cl ? ? 40 pf t wl t wh f pp t thl t isu t tlh t ih t odly input output 50% ? vdd t oh sdio_clk
document number: 002-15045 rev. *f page 37 of 44 advance cyw43143 13.6 usb parameters a. timing is based on cl 40 pf load on cmd and data. b. min(vih) = 0.7 vddio_sd and max(vil) = 0.2 vddio_sd. c. 0 - 46 mhz when running at 1.8v. table 23. usb parameters parameter symbol comments minimum typical maximum unit general baud rate bps ? ? 2.5 ? gbaud reference frequency fref from crystal oscillator ? 100 ? mhz reference clock amplitude vr ef lvpecl, ac coupled 1 ? ? v receiver differential termination zrx-diff-dc differential termination 80 100 120 ? dc impedance zrx-dc dc common-mode impedance 40 50 60 ? powered down termination zrx-high-imp-dc power-down high impedance (singled ended to ground) 200k ? ? ? input voltage vrx-diffp-p ac coupled, differential p-p 175 ? 1200 mv jitter tolerance trx-eye minimum receiver eye width 0.4 ? ? ui differential return loss rlrx-diff differential return loss 12 ? ? db common-mode return loss rlrx-cm common-mode return loss 11 ? ? db unexpected electrical idle enter detect threshold integration time trx-idel-det-diff- entertime an unexpected electrical idle must be recognized no longer than this time to signal an unexpected idle condition. ??10ms signal detect threshold vrx-idle-det- diffp-p electrical idle detect threshold 65 ? 175 mv transmitter output voltage vtx-diffp-p differential p-p, program- mable in 16 steps 0 ? 1200 mv output voltage rise time vtx-rise 20% to 80% 0.125 ? ? ui output voltage fall time vtx-fall 80% to 20% 0.125 ? ? ui de-emphasis (a1) vtx-de-ratio programmable in 16 steps 0 ? 40 % rx detection voltage swing vtx-rcv-detect the amount of voltage change allowed during receiver detection. ??600mv ac peak common-mode voltage vtx-cm-acp ac peak common-mode ripple ??20mv absolute delta of dc common-mode voltage during l0 and electrical idle vtx-cm-dc-active- idle-delta absolute delta of dc common-mode voltage during l0 and electrical idle. 0?100mv
document number: 002-15045 rev. *f page 38 of 44 advance cyw43143 absolute delta of dc common-model voltage between d+ and d- vtx-cm-dc-line- delta dc offset between d+ and d? 0?25mv electrical idle differential peak output voltage vtx-idle-diffp peak-to-peak voltage 0 ? 20 mv tx short circuit current itx-short current limit when tx output is shorted to ground. ??90ma differential termination ztx-diff-dc differential termination 80 100 120 ? differential return loss rltx-diff differential return loss 8 ? ? db common-mode return loss rltx-cm common-mode return loss 8?? db tx eye width ttx-eye minimum tx eye width 0.7 ? ? ui table 23. usb parameters (cont.) parameter symbol comments minimum typical maximum unit
document number: 002-15045 rev. *f page 39 of 44 advance cyw43143 14. thermal information note: ambient air temperature is 1 mm above the heat shield on top of the chip. ambient air temperature: ta = 65c, subject to absolute junction maximum temperature at 125c. the cyw43143 is designed and rated for operation at a maximum junction temperatur e not to exceed 125c. 14.1 junction temperature estimation and psi jt versus theta jc package thermal characterization parameter psi-j t ( ? jt ) yields a better estimation of actual junction temperature (t j ) versus using the junction-to-case thermal re sistance parameter theta-j c ( ? jc ). the reason for this is ? jc assumes that all the power is dissipated through the top surface of the package case. in actual applicat ions, some of the power is dissipated through the bottom and sid es of the package. ? jt takes into account power dissipated through the top, bottom, and sides of the package. the equation for calculating the device junction temperature is as follows: t j = t t + p ?? jt where: t j = junction temperature at steady-state condition, c t t = package case top center temperature at steady-state condition, c p = device power dissipation, watts ? jt = package thermal characteristics (no airflow), c/w table 24. 56-pin qfn thermal characteristics a a. 1s1p jedec board, package only, no heat sink, ta = 65c. p = 1.061w (pa on). air velocity m/s power w t j_max c t t c ? ja, c/w ? jt c/w 0 1.166 110.3 105.2 37.95 4.37
document number: 002-15045 rev. *f page 40 of 44 advance cyw43143 15. package information figure 7. 7 mm 7 mm, 56-pin qfn package
document number: 002-15045 rev. *f page 41 of 44 advance cyw43143 16. ordering information table 25. ordering information part number package ambient temperature BCM43143kmlg 7 mm 7 mm, 56-pin qfn (rohs compliant) 0 to 65c (32 to 149f)
document number: 002-15045 rev. *f page 42 of 44 advance cyw43143 document history document title: cyw43143 single-c hip ieee 802.11b/g/n mac/phy/radio with usb/sdio host interface document number: 002-15045 revision ecn orig. of change submission date description of change ** ? - 04/26/12 43143-ds100-r: initial release *a ? - 06/03/13 43143-ds101-r: added: ? various features on cover, reorganized feature lists. ? ?link power management (lpm) support? on page 16. ? ?i2s interface? on page 17. ? ?serial flash timing? on page 47. ? ?i2s slave mode tx timing? on page 48. ? updated: ? figure 1 on page 2. ? figure 3 on page 11. ? figure 4 on page 13. ? note in ?crystal os cillator? on page 15. ? figure 9 on page 24. ? table 2 on page 25. ? table 3 on page 26. ? table 4 on page 28. ? table 5 on page 32. ? table 6 on page 33. ? table 7 on page 34. ? table 9 on page 36. ? table 10 on page 37. ? table 11 on page 39. ? note in section 14: ?thermal information,? on page 56. ? table 24 on page 56 *b - - 06/25/13 43143-ds102-r: updated ? table 7 on page 34. *c - - 02/24/14 43143-ds103-r: updated: ? ?reset and low-power off mode? on page 12 ? table 6: ?absolute maxi mum ratings,? on page 30 ? table 8: ?wlan current consumption in sdio mode using sr_vddbat5v,? on page 32 ? table 9: ?wlan current consumption in usb mode using vdd33,? on page 33 ? table 16: ?2.4 ghz band transmitter rf specifications,? on page 40 ? section 14: ?thermal information,? on page 53
document number: 002-15045 rev. *f page 43 of 44 advance cyw43143 *d - - 11/14/14 43143-ds104-r: updated: ? table7:?guaranteed operat ing conditions and dc characteristics,? on page32. ? table8:?wlan current consumption in sdio mode using sr_vddbat5v,? on page33. ? table9:?wlan current consumption in usb mode using vdd33,? on page34. *e 5448745 utsv 09/28/2016 migrated to cypress template *f 5255423 aesatmp7 04/20/2017 updated cypress logo and copyright. document title: cyw43143 single-c hip ieee 802.11b/g/n mac/phy/radio with usb/sdio host interface document number: 002-15045
document number: 002-15045 rev. *f revised april 20, 2017 page 44 of 44 cyw43143 ? cypress semiconductor corporation, 2012-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information pr ovided in this document, includ ing any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? 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